1. Field of the Invention.
This invention generally relates to programmable logic circuits, and more particularly to a method for programming a field-programmable gate array with configuration data stored in a memory chip.
2. Description of the Related Art.
Integrated circuits known as programmable logic arrays (PLAs) employ a fixed number of logic gates, and sometimes flip-flop circuits, on a single chip to perform custom logic functions. Their appeal lies mainly in their versatility. A single PLA chip can, for example, perform the work of several single-function IC chips, thereby advantageously conserving space and reducing the cost and complexity of the overall system in which it is employed.
The logic gates of early PLAs were constructed from bipolar transistor elements arranged in an emitter-follower configuration on a silicon chip. Included in each transistor element was a nichrome fuse linking the emitter of the transistor to a bit line connecting the emitters of other gates in the array.
Programming these primitive PLAs was performed by the manufacturer using a hardware approach. Special programming equipment was used to blow fuses in selected gate-transistor elements according to a pattern that would satisfy a program table defining the combinational logic functions to be performed by the PLA.
This primitive form of PLA chip technology presented a number of disadvantages, not only in terms of their relatively low processing capability but also in terms of complications associated with programming them. For example, each PLA necessarily had to be programmed prior to its insertion into the system circuitry. This made standardization impossible because each chip essentially had to be custom made by the manufacturer, which added significantly to the time, cost, and complexity of the PLA manufacturing process.
Furthermore, because the fuse-blowing technique was essentially a destructive process, programming a PLA was often irreversible. In order to change the functionality of a PLA, the customer had to send it back to the manufacturer, who would then physically remove the PLA from the circuit, reprogram it by blowing a new fuse pattern, if possible, and reinsert it into the circuit. If reprogramming proved to be impossible, the manufacturer had to program and install a new chip into the system.
The development of electrically erasable gate-transistors significantly improved PLA performance and programming techniques, to the benefit of both the chip customer and chip manufacturer. With this technology, PLAs can achieve a lower part count, lower power dissipation, higher processing speed, and greater system flexibility compared with their more rudimentary ancestors.
Equally important, electrically erasable gates make it possible for PLAs to be programmed, after manufacture, using a software approach, which essentially involves transferring special data, known as configuration data, from an external memory into a memory built directly into the PLA chip. Once inside, the data is used to alter the electrical state of selected gates in the chip, in an manner analogous to blowing fuses, to achieve the desired logic configuration. Because this method of programming can be performed in the field, PLAs made from electrically erasable gates have come to be known as field-programmable gate arrays (FPGAs).
Various types of memories have been used for storing FPGA configuration dam. U.S. Pat. No. 5,249,164 to Koz, for example, discloses a system which uses a ROM chip to store FPGA configuration data.
There are, however, a number of drawbacks associated with using a ROM as an FPGA memory. For example, because a ROM chip cannot be programmed once it has been inserted into the system (i.e., it is not "in-circuit" programmable), programming of the ROM chip with FPGA configuration data must be performed by the manufacturer before installation into the system circuitry.
In addition, logic functions to be performed by the FPGA can be changed only by physically removing the ROM and either reprogramming it or replacing it with a new ROM chip loaded with different configuration data. In at least these respects, then, use of a ROM chip as an FPGA memory is, for all practical purposes, a throw back to the fuse blowing techniques previously discussed.
U.S. Pat. Nos. 5,150,048 and 5,243,273 to McAuliffe et at. disclose systems which use RAM chips as FPGA memories. Because a RAM is in-circuit programmable, the role of the chip manufacturer can be eliminated from the manufacturing loop. Advantageously, the customer himself can program the FPGA after the chip manufacturer has installed it into the system, by loading configuration data into the FPGA RAM. Moreover, the customer can change the functionality of the chip by reprogramming it with new configuration data. Other RAM-based FPGAs are disclosed in U.S. Pat. Nos. 5,361,373 and 4,870,302.
In spite of these advantages, the systems disclosed in the McAuliffe patents are not optimal because of inherent limitations associated with the use of a RAM as FPGA memory. For example, a RAM is a temporary storage device known as a static memory. Data stored within it remains there only for as long as power is being supplied it. As soon as the power is shut off, the entire contents of a RAM is lost. The static nature of an FPGA RAM therefore necessarily requires configuration data to be loaded into it every time power to the system is turned on. The associated delays and additional hardware required to load the RAM each time power is turned on adds significantly to the cost and complexity of the FPGA system.
From the foregoing discussion, it is evident that the performance of FPGA systems, and the methods used to program them, are now limited less by the hardware limitations of the FPGA chips themselves, and more by limitations associated with the memory used to store FPGA configuration data, and, as will now be explained, by limitations associated with other FPGA system hardware components.
Over the past 30 years, there has been an exponential growth in transistor speed and in the number of transistors per chip. Chip interconnection speeds and I/O counts, however, have failed to increase at a commensurate rate, thereby preventing the performance of integrated circuits from reaching their full potential.
The inability of chip packaging technology to keep pace has also limited FPGA performance. External leads on conventional through-hole and surface mount IC packages degrade performance because they have associated with them parasitic capacitances and inductances which distort the shape of the signals passing through them.
Recent advances in packaging and interconnection technologies have improved IC performance. This may be best exemplified by the multichip module (MCM).
Generally speaking, an MCM includes two or more bare integrated circuit chips, often referred to as "dies," mounted on a common circuit base. The dies are interconnected by signal, power, and ground wires incorporated within the base. Each die contains a plurality of bonding pads along its periphery which function as input/output (I/O) terminals for the integrated circuit contained therein. Very fine wires, typically a fraction of a millimeter in diameter, are used to establish electrical connection between the bonding pads and the wires in the base. All of the aforementioned components are then encapsulated within an outer protective packaging, which then may be mounted on a printed wiring board to establish electrical connection with system circuitry. Microchip modules are disclosed in the publication Microchip Module Technologies and Alternatives by Doane and Franzon, Van Nostrand Reinhold publisher, and in U.S. Pat. Nos. 5,271,887 and 5,432,708.
The MCM packaging philosophy reduces the average spacing between ICs in an electronic system to achieve a myriad of advantages over conventional IC packages. MCM packages, for example, are substantially smaller in size and therefore take up less board space within the system circuit. MCM packages also require comparatively fewer chip connections and interconnections. This, in turn, translates into a reduction in parasitic capacitances and inductances and signal delays, all of which increase overall system speed and reliability.
MCM packages containing logic circuits such as those typically found in FPGAs have been disclosed. See, for example, U.S. Pat. No. 5,432,708. No prior art reference, however, teaches or suggests an MCM equipped with FPGA and an FPGA memory dies for performing one or more system functions, nor has there been disclosed a method for programming and reprogramming such a system.
It is therefore clear, based on the foregoing discussion, that there are at least two long-felt needs which have been left unsatisfied by the prior art.
The first relates to memories for holding configuration data for programming an FPGA. Systems which use ROM-based FPGA memories, while advantageously non-volatile, have proven to be inadequate because they are not in-circuit programmable. RAM-based FPGA memories, while in-circuit programmable, are inefficient because they need to be reprogrammed every time the system power is turned on. Thus, there is a need for the selection of an FPGA memory that will optimize the overall performance of the system in which it is employed, and further one which will improve the speed, cost, and efficiency of programming and reprogramming such a system.
Second, there is a need for FPGA-based system which has improved speed and performance realized by incorporating the FPGA and FPGA memory in die form within an MCM package.